J-Link is a USB powered JTAG emulator for ARM cores. It connects via USB to the Windows (2000/XP/Vista) PC host.

Features: USB 2.0 interface Any ARM7/ARM9/ARM11, Cortex™-M3 core supported, including thumb mode Serial Wire Debug (SWD) supported * Serial Wire Viewer (SWV) supported * Automatic core recognition Maximum JTAG speed 12 MHz Download speed up to 720 Kbytes/second ** DCC speed up to 800 Kbytes/second ** Seamless integration into the IAR Embedded Workbench® IDE No power supply required, powered through USB Support for adaptive clocking All JTAG signals can be monitored, target voltage can be measured Support for multiple devices Fully plug and play compatible Standard 20-pin JTAG connector Wide target voltage range: 1.2V - 3.3V, 5V tolerant USB and 20-pin ribbon cable included Memory viewer (J-Mem) included TCP/IP server included, which allows using J-Link via TCP/IP networks RDI interface available, which allows using J-Link with RDI compliant software Flash programming software (J-Flash) available Flash DLL available, which allows using flash functionality in custom applications Software Developer Kit (SDK) available Embedded Trace Buffer (ETB) support Adapter for 5V JTAG targets available 14-pin JTAG adapter available Optical isolation adapter available Target power supply: J-Link can supply up to 300 mA to target with overload protection * = Supported since J-Link hardware version 6 ** = Measured with J-Link Rev.5, ARM7 @ 50 MHz, 12MHz JTAG speed. Download J-Link software

Available software packages

J-Link ARM download speed

The following table lists J-Link ARM performance values (kByte/s) for writing to memory (RAM):

Please note that the actual speed depends on various factors, such as JTAG, clock speed, host CPU core etc.

JTAG Speed

There are basically three types of speed settings:

• Fixed JTAG speed
• Automatic JTAG speed
• Adaptive clocking

Fixed JTAG speed

The target is clocked at a fixed clock speed. The maximum JTAG speed the target can handle depends on the target itself. In general ARM cores without JTAG synchronization logic (such as ARM7-TDMI) can handle JTAG speeds up to the CPU speed, ARM cores with JTAG synchronization logic (such as ARM7-TDMI-S, ARM946E-S, ARM966EJ-S) can handle JTAG speeds up to 1/6 of the CPU speed. JTAG speeds of more than 10 MHz are not recommended.

Automatic JTAG speed

Selects the maximum JTAG speed handled by the TAP controller.

NOTE:
On ARM cores without synchronization logic, this may not work reliably, since the CPU core may be clocked slower than the maximum JTAG speed.

Adaptive clocking

If the target provides the RTCK signal, select the adaptive clocking function to syn- chronize the clock to the processor clock outside the core. This ensures there are no synchronization problems over the JTAG interface.

NOTE:
If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization requirements result in a lower maximum clock frequency than with non-adaptive clocking. Do not use adaptive clocking unless it is required by the hardware design.

Using J-Link

Installing the kernel mode driver
In order to use J-Link, a the kernel mode USB driver jlink.sys needs to be installed. This is done by right clicking on the jlink.inf file and selecting "Install" from the context menu, or by connecting J-Link to a USB port of the Host PC and then referring to the inf file. An installation utility is to come up soon.

Checking functionality

The Jlink.exe file can be used to connect to the ARM chip. It currently permits only simple commands, such as memory dump, halt, step, go, Id-check. This can be used to verify proper installation of the USB driver and to verify the connection to the ARM chip, as well as for simple analysis of the target system.

JTAG interface connection (20 pin)

There is a standard 20 pin connector defined by ARM. J-Link ARM has a built-in 20-pin JTAG connector, which is compatible with this standard.

JTAG interface connector signals :

Notes

All pins marked NC are not connected inside J-Link. Any signal can be applied here; J-Link will simply ignore such a signal.

All GND pins must be connected to 0V on the target board.

Pin 19 (VCCS) is used to supply J-Link's target interface. J-Link itself is USB powered, only the target interface is powered thru this pin. Should be connected to target CPUs supply voltage (VCC) and should be between 1.8 and 3.3 V.

Pin 2 is not connected inside J-Link. A lot of targets have pin 1 and pin 2 connected. Some targets use pin 2 instead of pin 1 to supply VCC. These targets will not work with J-Link, unless Pin 1 and Pin 2 are connected on the target's JTAG connector.

Pin 3 (TRST) should be connected to target CPUs TRST pin (sometimes called NTRST). J-Link will also work if this pin is not connected, but you may experience some limitations when debugging. TRST should be separate from the CPU Reset (pin 15)

Pin 11 (RTCK) should be connected to RTCK if available, otherwise to GND.

SWD and SWO/SWV (also called SWV) compability

SWD overview

The J-Link and J-Trace support ARMs Serial Wire Debug (SWD). SWD replaces the 5-pin JTAG port with a clock (SWDCLK) and a single bi-directional data pin (SWDIO), providing all the normal JTAG debug and test functionality. SWDIO and SWCLK are overlaid on the TMS and TCK pins. In order to communicate with a SWD device, J-Link sends out data on SWDIO, syn- chronous to the SWCLK. With every rising edge of SWCLK, one bit of data is trans- mitted or received on the SWDIO. The data read from SWDIO can than be retrieved from the input buffer.

SWD connector pinout

The following table shows the SWD pinout:

Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

Serial Wire Output (SWO) overview

J-Link can be used with devices that supports Serial Wire Output (SWO). Serial Wire Output (SWO) support means support for a single pin output signal from the core. It is currently tested with Cortex-M3 only.

Supported SWO speeds

The supported SWO speeds depend on the connected emulator. They can be retrieved from the emulator. Currently, the following are supported:

Serial Wire Viewer (SWV) overview

The Instrumentation Trace Macrocell (ITM) and Serial Wire Output (SWO) can be used to form a Serial Wire Viewer (SWV). The Serial Wire Viewer provides a low cost method of obtaining information from inside the MCU. The SWO can output trace data in two output formats, but only one output mechanism is valid at any one time. The 2 defined encodings are UART and Manchester. The current J-Link implementation sup- ports only UART encoding. Serial Wire Viewer uses the SWO pin to transmit different packets for different types of information. The three sources in the Cortex-M3 core which can output information via this pin are:

• Instrumentation Trace Macrocell (ITM) for application-driven trace source that supports printf-style debugging. It supports 32 different channels, which allow it to be used for other purposes such as real-time kernel information as well.
• Data Watchpoint and Trace (DWT) for real-time variable monitoring and PC-sampling, which can in turn be used to periodically output the PC or various CPU-internal counters, which can be used to obtain profiling information from the target.
• Timestamping. Timestamps are emitted relative to packets.

Further application documents

Refer to the following documents for detailed information about SWO/SWV:

Multiple devices in the scan chain

J-Link ARM can handle multiple devices in the scan chain. This applies to hardware where multiple chips are connected to the same JTAG connector. As can be seen in the drawing below, the TCK and TMS lines of all JTAG device are connected, while the TDI and TDO lines form a bus. Currently, up to 8 devices in the scan chain are supported. One or more of these devices can be ARM cores; the other devices can be of any other type but need to comply with the JTAG standard.

Multi core debugging

J-Link is able to debug multiple cores on one target system connected to the same scan chain.

How multi-core debugging works Multi-core debugging requires multiple debuggers or multiple instances of the same debugger. Two or more debuggers can use the same J-Link / J-Trace simultaneously. Configuring a debugger to work with a core in a multi-core environment does not require special settings. All that is required is proper setup of the scan chain for each debugger. This enables J-Link / J-Trace to debug more than one core on a target at the same time. Both debuggers share the same physical connection.

J-Link TCP/IP Server

It allows using the J-Link via TCP/IP, which allows connecting to and fully using a J-Link connected to the USB port of an other computer. Performance is just slightly (about 10%) lower than with direct USB connection. The J-Link server is free and included in the software package available for download.

Specifications

Software download