The J-Link DLL is a standard Windows DLL typically used from "C" (Visual Basic or Delphi projects are also doable). It makes the entire functionality of J-Link available thru the exported functions. The functionality includes things such as halting/stepping the ARM core, reading/ writing CPU and ICE registers and reading / writing memory. Therefore it can be used in any kind of application accessing an ARM core. Sample applications are a memory viewer, DCC communication program, Debugger or flash programming tool, such as J-Flash as well as a small command line program Jlink.exe, which is also available in source code form.The standard DLL does not have API functions for flash programming. However, the functionality offered can be used to program the flash. In that case a flashloader is required.

What do I need to write my own program with J-Link?

The J-Link SDK is needed if you want to write your own program with J-Link. The listed files in the table below are included in the J-Link SDK. For more information on how to obtain a license please contact info@segger.com.

Requirements

The following items are required to develop software for J-Link:

• PC running Win2K or XP
• J-Link A RM
• ARM target system
• x86 compiler, linker, opt. IDE

Development environment (compiler)

Any "C/C++" compiler will do. Workspace (Project) file is for Microsoft Visual Studio (V6.0) or Visual Studio .net (V7.0 or newer).
Other compilers will work as well, but no example workspace is provided.

Data types

Since "C" does not provide data types of fixed lengths which are identical on all plat- forms, the JLinkARM.DLL uses, in most cases, its own data types:

ARM core / JTAG Basics

The ARM 7 and ARM 9 architecture is based on Reduced Instruction Set Computer (RISC) principles. The instruction set and related decode mechanism are greatly sim- plified compared with microprogrammed Complex Instruction Set Computers (CISCs).

JTAG

JTAG is short for Joint Test Action Group. In the scope of this document, "the JTAG standard" means compliance with IEEE Standard 1149.1-2001.

Test access port (TAP)

JTAG defines a TAP (Test access port). The TAP is a general-purpose port that can provide access to many test support func- tions built into a component. It is composed as a minimum of the three input connec- tions (TDI, TCK, TMS) and one output connection (TDO). An optional fourth input connection (nTRST) provides for asynchronous initialization of the test logic.

The TAP controller

The TAP controller is a synchronous finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry.Diagram and detailed descriptions of the individual states can be found in IEEE stan- dard 1149.1-2001.

The ARM core

The ARM7 family is a range of low-power 32-bit RISC microprocessor cores. Offering up to 130MIPs (Dhrystone2.1), the ARM7 family incorporates the Thumb 16-bit instruction set. The family consists of the ARM7TDMI, ARM7TDMI-S and ARM7EJ-S processor cores and the ARM720T cached processor macrocell.
The ARM9 family is built around the ARM9TDMI processor core and incorporates the 16-bit Thumb instruction set. The ARM9 Thumb family includes the ARM920T and ARM922T cached processor macrocells.

Processor modes

The ARM architecture supports seven prcessor modes.

Registers of the CPU core

The CPU core has the following registers:

The ARM core has a total of 37 registers:

• 31 general-purpose registers, including a program counter. These registers are 32 bits wide.
• 6 status registers. These are also 32 bits wide, but only 32 bits are allocated or need to be implemented.

Registers are arranged in partially overlapping banks, with a different register bank for each processor mode. At any time, 15 general-purpose registers (R0 to R14), on or two status registers and the program counter are visible.

ARM /Thumb instruction set

An ARM core starts execution in ARM mode after reset or any type of exception. Most (but not all) ARM cores come with a secondary instruction set, called the Thumb instruction set. The core is said to be in Thumb mode if it is using the thumb instruction set. The thumb instruction set consists of 16-bit instructions, where the ARM instruction set consists of 32-bit instructions. Thumb mode improves code density by app. 35%, but reduces execution speed on systems with high memory bandwidth (because more instructions are required). On systems with low memory bandwidth, Thumb mode can actually be as fast or faster than ARM mode. Mixing ARM and Thumb code (interworking) is possible. J-Link fully supports debugging of both modes without limitation.

EmbeddedICE

EmbeddedICE is a set of registers and comparators used to generate debug exceptions (such as breakpoints). EmbeddedICE is programmed in a serial fashion using the ARM core controller. It consists of two real-time watchpoint units, together with a control and status register. You can program one or both watchpoint units to halt the execution of instructions by ARM core. Two independent registers, debug control and debug status, provide overall control of EmbeddedICE operation.
Execution is halted when a match occurs between the values programmed into EmbeddedICE and the values currently appearing on the address bus, data bus, and various control signals. Any bit can be masked so that its value does not affect the comparsion.
Either of the two real time watchpoint units can be configured to be a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). You can make watchpoints and breakpoints data-dependent.

EmbeddedICE is additional debug hardware within the core, therefore the Embed- dedICE debug architecture requires almost no target resources (for example, mem- ory, access to exception vectors, and time).

Breakpoints

A "breakpoint" stops the core when a selected instruction is executed. It is then possible to examine the contents of both memory (and variables).

Watchpoints

A "watchpoint" stops the core if a selected memory location is accessed. For a watchpoint (WP), the following properties can be specified:

• Address (including address mask)
• Type of access (R, R/W, W)
• Data ( including d ata m ask)

Software / hardware breakpoints

Hardware breakpoints are "real" breakpoints, using one of the 2 available watchpoint units to breakpoint the instruction at any given address. Hardware breakpoints can be set in any type of memory (RAM, ROM, Flash) and also work with self-modifying code. Unfortunately, there are only a limited number of these available (2 in the EmbeddedIce). When debugging a program located in RAM, an other option is to use software breakpoints. With software breakpoints, the instruction in memory is modified. This does not work when debugging programs located in ROM or Flash, but has one huge advantage: The number of software breakpoints is not limited.

The ICE registers

The two watchpoint units, known as watchpoint 0 and watchpoint 1. Each contains three pairs of registers:

• address value and address mask
• data value and data mask
• control value and control mask

The following table shows the function and mapping of EmbeddedICE registers.

For more informations about EmbeddedICE see the technical reference manual of your ARM CPU. (www.arm.com)

Using the sample application

The sample application can be used to test the correct installation and proper function of the JLinkARM.
The PC sample application first tries to establish a connection to the target by opening the device. If this fails, an error message is shown. If a connection can be established, the sample application shows the Id of the ARM core and starts some writing and reading operations.
The sample application is supplied in source code form. To run the sample application, you have to compile it with an ANSI "C" compiler. A project workspace of the sample application for Microsoft Visual C++ 6.0 or Microsoft Visual .Net is supplied.

Compiling and running the sample application

Open the project workspace with a double click on JLink.dsw und compile the source with Build|Build JLink.exe (Shortcut: F7) and run the executable with Build|Execute JLink.exe (Shortcut: CTRL-F5) from the menu.

If the connection to the J-Link-ARM works correctly, the JLink.exe will show some status informations.

JLink.exe is a tool, that can be used to verify proper installation of the USB driver and to verify the connection to the ARM chip, as well as for simple analysis of the target system. It permits some simple commands, such as memory dump, halt, step, go and Id-check, as well as some more in-depths analysis of the the state of the ARM core and the ICE breaker module.

Most important commands

f - Show firmware info

Shows the firmware info. Normally, the firmware is updated automatically by the DLL.

i - Show JTAG Id

Shows the JTAG Id.
Sample output below:
JTAG Id: 0x1F0F0F0F Version: 0x1 Part no: 0xf0f0 Man. Id: 0787

w2 / w4 - Write into memory

Allows writing of arbitrary values into the target memory in units of 16 or 32 bits.

Ice - Show state of the embedded ice macrocell (ICE breaker)

Shows the contents of all ICE registers, along with some basic explanations.
Sample output below:

wi - Write ice register

Allows writing into individual ICE registers for test purposes.

regs - Show core registers

Shows the contents of all CPU core registers.

Software download