SEGGER Evaluation Software for NXP LPCXpresso 55S69

Product	Supported features
emPower OS
embOS	Core + Profiling
emCompress	emCompress-Embed
emCrypt	PRO
emFile	BASE + Encryption, FAT, Journaling, MMC/SD, NAND, RAMDisk
emModbus	Master + Slave
emNet	BASE + CoAP Server / Client, DHCP Server, (m)DNS/LLMNR/DNS-SD Server, FTP Client, FTP Server, MQTT Client, NetBIOS Name Service, SMTP Client, SNMP Agent, SNTP Client, UPnP, WebSocket, emNet driver for Freescale Kinetis
emSecure	emSecure-RSA, emSecure-ECDSA
emSSH	Secure Shell software library
emSSL	Secure Sockets Layer
emUSB-Device	BASE + Bulk, CDC, HID, MSD, MSD-CDROM, MTP, Printer Class, IP-over-USB component, Target Driver for Freescale Kinetis HighSpeed (EHCI)
emUSB-Host	BASE + CDC, FTDI UART, HID, MSD, MTP, Printer Class, Freescale Kinetis FullSpeed Driver
emWeb	Web Server
emWin	BASE + AntiAliasing, Bitmap Converter, Font Converter, Memory Devices, Simulation, VNC Server, Widgets, Window Manager, GUIDRV_FlexColor
IoT Toolkit	HTTP Client, JSON Parser

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LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz
Micro SD card slot (4-bit SDIO)
Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link protocol options
UART and SPI port bridging from LPC55S69 target to USB via the onboard debug probe
High and full speed USB ports with micro A/B connector for host or device functionality
Hardware support for external debug probe
NXP MMA8652FCR1 accelerometer
Stereo audio codec with line in/out
MikroEletronika Click expansion option
LPCXpresso-V3 expansion option compatible with Arduino UNO
PMod compatible expansion / host connector
3 x user LEDs, plus Reset, ISP (3) and user buttons

Arm Cortex-M33 processor, running at a frequency of up to 100 MHz
TrustZone, Floating Point Unit (FPU) and Memory Protection Unit (MPU)
Arm Cortex-M33 built-in Nested Vectored Interrupt Controller (NVIC)
Non-maskable Interrupt (NMI) input with a selection of sources
Arm Cortex-M33 co-processor
Up to 640 KB on-chip flash program memory with a flash accelerator and 256-byte page erase and write
Up to 320 KB total SRAM consisting of 288 KB on the system bus and 32 KB on Core Bus
AES-256 encryption/decryption engine
Secure Hash Algorithm (SHA2) module supporting secure boot with dedicated DMA controller
Physical Unclonable Function(PUF) using dedicated SRAM for silicon fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes hardware for key extraction