SEGGER Microcontroller, a leading supplier of software, hardware and development tools for embedded systems, and SiFive, the first fabless provider of customized, open- source-enabled semiconductors, today announced the availability of SEGGER J-Link support for SiFive Coreplex IP, based on the RISC-V architecture. The growing interest in Coreplex IP is increasingly prompting vendors like SEGGER to make its industry leading tools available as part of the RISC-V ecosystem.

RISC-V was born from the dire need to address the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures, a result of the economic demise of Moore's Law. SiFive was founded by the inventors of RISC-V – Yunsup Lee, Andrew Waterman and Krste Asanovic – with a mission to democratize access to custom silicon. In its first six months of availability, its HiFive1 software development boards have been delivered to thousands of developers in over 40 countries, making SiFive Coreplex IP the de facto leader for RISC-V cores, with more public customers, working silicon and development boards than any other RISC-V vendor.

"In order to bring RISC-V and custom silicon to its full potential, the ecosystem needs a full complement of established commercial tools with which to validate designs," said Jack Kang, vice president of product and business development at SiFive. "Support from SEGGER's industry-leading J-Link debug probe family is a huge step for embedded developers who wish to debug software and production program chips using RISC-V cores. We look forward to our continued partnership with SEGGER and are excited to see how this development impacts the entire RISC-V community."

All current J-Link models now support debugging of RV32 RISC-V cores. This includes support from SEGGER's GDB Server, which is part of the J-Link software package that supports SiFive's free Eclipse-based Freedom Studio. J-Link's high performance and functionality allows it to be easily used and it provides reliable, professional support to RISC-V cores. Features also include a direct Flash memory download via an open flash loader interface giving SiFive and the RISC- V ecosystem access to SEGGER's vast catalog of supported flash devices. For systems running code from flash memory instead of RAM, there is an unlimited number of breakpoints not only in RAM, but also in Flash (with higher end J-Link PLUS, J-Link Ultra+ and J-Link PRO models).

"RISC-V is a great CPU architecture. With various open-source and commercial implementations, we believe that it will become very popular, very fast," said Alex Grüner, J-Link product manager and CTO of SEGGER. "J-Link’s family of professional debug probes are now available to help contribute to and build on the success of RISC-V." said Rick O’Connor, chairman of the RISC-V Foundation: "The fact that SEGGER is seeing commercial demand for RISC-V is evidence that open-source semiconductors are enabling a new wave of silicon design. SiFive and others implementing RISC-V cores based on SiFive's Coreplex IP will now have the necessary tools to simplify their development workflow."

The low-cost version J-Link EDU allows students and hobbyists to use professional debug technology with RISC-V. Using J-Link with RISC-V is easy – download examples here.

More information about J-Link can be found here.

For more information on the SiFive's Coreplex IP, click here.